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Figure 2. A buswire test can be used to diagnose open faults at the pin level. Additionally, tests for AC-coupled signals can be integrated with interconnect and buswire tests in systems with IEEE Special tests can also be used to check pull-up and pull-down resistors, ensuring that resistors are present in the assembled system in addition to testing the nets for open and short faults.
To accomplish this, resistors are tested by first driving the signal to a state opposite the pulled value. The net is then tri-stated, allowing the resistor to pull the signal back to the original state. Finally, the signal is sampled and the value is compared to the expected pulled value. Not only can interconnections between boundary-scan components and simple transparent components be tested, but additional non-boundary-scan components can be controlled and tested for functionality and continuity using connected boundary-scan components.
Simple test patterns may be used to test logic devices such as decoders or multiplexers, while sophisticated scripts may be used control and test complex devices for basic or advanced functionality, including analog-to-digital converters, UARTs, and Ethernet PHYs. A common application of a cluster tests uses the storage capability of RAM devices to verify interconnects between a boundary-scan device and a connected memory.
Using a model of the memory component, tests can be automatically created to write specific data patterns to memory addresses and then read back and compared against the expected value. These patterns are designed to ensure that all memory data and address signals are driven to both high and low logic states. Boundary-scan technology is commonly applied to product design, prototype debugging, and field service. The same test suite used to validate design testability can adapted and utilized for board bring-up, high-volume manufacturing test, troubleshooting and repairs, and even field service and reprogramming.
Figure 3. Memory interconnects are tested using a connected boundary-scan device. Using this same interface, the JTAG port can be used to initialize a processor, download and run a test program, and then obtain results; this test technique is a fast, convenient method for developing and executing peripheral tests and in-system-programming operations in embedded systems. Because these tests run at the system processor speed, defects that may not be identified during low-speed execution can be detected.
To program flash devices, the pins of a connected boundary-scan-compatible component can be used to control the memory and erase, program, and verify the component using the boundary-scan chain.
In these cases, a small flash programming application is downloaded to the controlling device over the JTAG port, which is then used to interface between the test system and the flash programming application running on the embedded system.
The program can run at much higher speeds than boundary-scan, increasing production throughput and rivaling or surpassing the speeds of USB and Ethernet-based programming solutions, without requiring an operating system or high-level software be present on the embedded system.
The IEEE We have received your request and would like to thank you for contacting us. We will get back to you as soon as possible. June 15, by. Training Corelis offers free three-day training classes with a boundary-scan tutorial and hands-on lab exercises using Corelis ScanExpress hardware and software. Tutorials Our tutorials feature an overview of JTAG, related technologies, and new technology trends for reducing costs, speeding test development, and improving quality.
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